In semiconductor processing technology, transistors and other electrical components are fabricated on a suitable substrate and interconnected to form integrated circuits (ICs), which perform numerous useful functions. The transistors and other devices are typically interconnected with each other and external circuitry by multiple layers of metal lines and through vias which are formed over the transistors and other devices. In some applications, each layer of metal lines has larger and thicker lines as they are stacked over the transistors, such that the first layer has the smallest metal lines and the last layer has the largest metal lines. The metal lines and vias are often surrounded by dielectric materials that provide insulation and reduce capacitance between adjacent lines. Frequently, the last layer of metal lines are contacted by vias and bumps such that the IC can be flip-chip connected to a package substrate having external circuitry.
To reduce the resistance of the metal lines and to thereby reduce voltage drop in the IC, thicker metal lines have been proposed, particularly in those layers that are higher in the stack over the transistors, and often for those at the highest layer in the stack. Incorporating thicker metal lines at or near the highest stack layer has numerous difficulties. In some current processes, for example, a single photosensitive dielectric material is formed over the metal lines, and then the dielectric material is patterned to open via holes for contact to the metal lines. For successful fabrication, the photosensitive dielectric material must provide sufficient planarity over the metal lines to provide a relatively flat surface (without bulges over the metal lines) and must be able to be patterned to the necessarily small dimensions required to contact the metal lines. However, for thick metal lines, currently available materials either do not provide adequate planarity, or they cannot be patterned to sufficiently small dimensions. Further, many of the proposed materials do not provide the mechanical strength necessary to reliably flip-chip package the IC to a package substrate.